1. Field of the Invention
The present invention relates to a serial communication control circuit.
2. Description of the Related Art
Serial communication may be employed for transferring various items of data between a piece of industrial equipment such as working machine or robot and a control device for controlling the same. At this time, an encoding scheme such as 4B5B or 8B10B is employed as an encoding scheme for generating a data reproduction clock from received data.
4B5B represents 4-bit data in 5-bit symbol data, and is configured such that at least one 1 is present in 5-bit symbol and the same values are not consecutive for more than 4 bits together with NRZI. 8B10B is such that 8-bit data is divided into upper 3 bits and lower 5 bits, 3B4B conversion for converting 3-bit data into 4-bit symbol data is performed on the upper 3 bits, 5B6B conversion for converting 5-bit data into 6-bit symbol data is performed on the lower 5 bits, and the respectively resultant items of 4-bit and 6-bit data are combined to be 10-bit symbol data. Thereby, the same bits are consecutive for 5 bits or less so that spread of a signal frequency is restricted and stability is improved.
The data subjected to the encoding is designed such that a ratio of the numbers of 0s and is contained in a series of transfer data set is totally kept equal. In the following, the ratio of time occupied by “1” in the series of transfer data set may be denoted as mark ratio (%). A state in which the numbers of is and 0s contained in the series of data set are equal may be called DC balance.
10-bit symbol data in 8B10B may contain five 1s and five 0s, may contain six 1s and four 0s, or may contain four is and six 0s. 8B10B has a running disparity function in which a code to be next transmitted is selected such that the DC balance is kept in consideration of the accumulative numbers of previously transmitted 1s and 0s. However, 4B5B does not have such a function, and if the same transmission data continues, the differences in the numbers of 1s and 0s are accumulated and the DC balance cannot be perfectly kept.
JP 2012-54870 A discloses that when a reception circuit receives data with a high or low mark ratio, pulse output is consequently distorted as a result of controlling a threshold to be higher or lower, and data with a high or low mark ratio needs to be transmitted and received for a sufficiently long time in order to acquire deterioration determination information when the distortion of pulse output is the largest.
Serial communication may utilize an AC coupling, or capacitive coupling termination form in which capacitors are inserted in series on a data signal line in order to secure specifications' compatibility or to enhance a noise margin. In the AC coupling, if the DC balance cannot be kept, an average level of the signal cannot be kept at a half voltage of the amplitude, and signal jitters may increase on the reception side.
With the technique disclosed in JP 2012-54870 A, a deteriorated site can be determined by phase data determination, but a mark ratio of data is not adjusted and thus reception signal's jitters may increase.